EDN

A robust scan insertion methodology

In the modern era, where meeting high performance and low power targets for any complex SoC (System on Chip) is very tough, testing the SoC has become even more challenging. The purpose of several DFT ...
Electronic Design

Implementing a Boundary Scan Methodology

When a global provider of air traffic, navigation, and landing system solutions began implementing its next-generation system, limitations of an existing test and debug methodology directly impacted ...
Electronic Design

A Methodology to Speed DFT Signoff

Shipping high-quality ICs requires that design-for-test (DFT) methodologies be included in a design. DFT provides external access at the device’s I/O pins to internal registers to either control or ...
Design-Reuse

Shift Power Reduction Methods and Effectiveness for Testability in ASIC

The recent increase in the technology usage and the competition to acquire global market has cornered the industry to move into lower Technological nodes with higher increase in Transistor’s per die, ...
Design-Reuse

DeFacTo Unveils New Design for Test Product that Eliminates Need for Gate-level Scan; Creates Industry's First High-level DFT Sign-off Methodology

HiDFT-Scan Analyzes, Implements Scan Test Structures in Register-Transfer Level Designs; Closes Historical Gap between RTL and DFT PALO ALTO, Calif.--October 22, 2007--DeFacTo Technologies today ...