A simple, out-of-order RISC-V processor simulator implementing the Tomasulo algorithm for dynamic instruction scheduling. RISC-V-Sim/ ├── src/ │ ├── main.cpp # Main entry point │ ├── include/ # Header ...
(VHDL, ModelSim, Xilinx) Simulated and synthesized a processor with a clock frequency of 25 MHz. Used Tomasulo algorithm to dynamically schedule instructions and execute them in out of program order ...
This repository documents a project for the "Computer System Architecture" course at Tongji University. It details the design, implementation, and analysis of a processor featuring dynamic scheduling, ...
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