Test compression offers the benefits of higher quality and lower test cost, but how do you choose the best methodology and tools for your current and future designs? Test compression evaluations ...

Test compression technology was invented to address the problem of escalating test-pattern size. Compression allows more test vectors to be applied to an IC in a shorter time and with fewer tester ...

Small geometries have projected IC technology into an era where test has become a crucial part in the chip design process and have introduced new challenges needing solutions that use already ...

In New test points slash ATPG test pattern count, I described a new type of test point technology used with scan compression for device testing. The key benefit of using test points with embedded ...

For the past five years, the cost of test has prevailed as the hottest topic in test. During this period, automated test equipment (ATE) has made a dramatic move towards low-cost design for test (DFT) ...

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

Large digital integrated circuits are becoming harder to test in a time- and cost-efficient manner. AI chips, in particular, have tiled architectures that are putting pressure on older testing ...