This repository contains a fully manually-written bare-metal project for the BL602 single-core RISC-V (SiFive E24), without using Bouffalo Lab's SDK. It features a clear and easy-to-understand ...

The enthusiasm for RISC-V suggests that the architecture is a force to be reckoned with. This makes the architecture a good investment in many cases. As you take up RISC-V assembler language, you can ...

This repository presents a structured collection of C programming exercises developed and tested on the RVfpga educational platform, using the Nexys A7 board powered by a RISC-V soft processor core.

SEGGER has released a new Open Flashloader for RISC-V systems, which can be adjusted to fit any RISC-V system, allowing engineers to write flash loaders which fit into just 2kB of RAM. This enables ...

Abstract: This paper presents a detailed description of the design of a 64-bit RISC-V processor that implements the RISC-VISA using Verilog hardware descriptive language. The design is simulated using ...

January 12, 2021-- SEGGER just released a new Open Flashloader for RISC-V systems. The template, which can be adjusted to fit any RISC-V system, allows engineers to write flash loaders which fit into ...

The LM3914 LED bar graph driver was an amazing chip back in the day. Along with the LM3915, its logarithmic cousin, these chips gave a modern look to projects, allowing dancing LEDs to stand in for a ...

If you wanted to make a CPU, and you’re not AMD or Intel, there are two real choices: ARM and RISC-V. But what are the differences between the two, and why do companies choose one over the other?

When the Meltdown and Spectre vulnerabilities were first uncovered in 2018, they heralded an industry-wide shift in perspective regarding processor security. As the IBM X-Force Threat Intelligence ...