EDN

SOC-PLL design requires trade-offs

PLLs (phase-locked loops) are common analogcircuits in SOCs (systems on chips). Almost allSOCs with a clock rate greater than 30 MHzuse a PLL for frequency synthesis. However, a“one-size-fits-all” PLL ...
EDN

Tracking PLL design through the decades, part 1

PLLs (phase-locked loops) are among the most commontypes of analog/mixed-signal circuits on today’sSOC (system-on-chip) ICs. PLLs are essential companionsto the digital-logic circuits and processorson ...
Electronics Weekly

Analogue or digital in PLL design

The performance of analogue phase-locked loops (PLLs) has steadily improved with operating frequencies extending to 8GHz and beyond. Recently, digital PLLs based on direct digital synthesis (DDS) have ...
Electronic Design

Smaller PLL Synthesizers Become Design-Friendlier

Phase-locked-loop (PLL) frequency synthesizers are signal sources often employed in many types of electronic equipment. They show up as clock sources in high-frequency instruments and as local ...
Design-Reuse

Is there a "one-size fits all" SOC PLL?

A PLL (phase-locked loop) is perhaps the most widely used analog circuit in SOCs (system-on-a-chip). Almost all SOCs with a clock rate over 30MHz use a PLL for frequency synthesis. Most SOCs use more ...
eeworldonline

What is a PLL for analog signals?

A phase-locked loop (PLL) for analog signals generates an output with a phase that’s precisely matched to the phase of an input reference. Analog PLLs are widely used in high-frequency applications ...
Electronic Design

PLL Cleans, Multiplies And Divides Input Frequencies

It is a fully functioning PLL subsystem for multiplying, dividing and cleaning input frequencies. Housed in a hermetically-sealed 7-pin DIL package, the PLL operates from a 4.5 to 5.5 Vdc supply, ...
The Engineer

Revolution and Evolution in Frequency Synthesis: How PLL/VCO Technology Has Increased Performance, Decreased Size, and Simplified Design Cycle

Microwave frequency generation has posed significant challenges to engineers over the years, requiring in-depth knowledge of analog, digital, and radio frequency (RF) and microwave ...
Electronics Weekly

ParthusCeva expands PLL design licensing website

Technology licensing firm ParthusCeva has expanded its website for phase locked loop (PLL) design, adding ‘ready-to-go’ PLLs and support for TSMC’s 0.13µm process. The site, PLLXpert Online, was ...
Design-Reuse

Parthus Technologies Announces a Breakthrough in PLL IP Delivery, Putting Design of Custom Clock Synthesis Cores in the Hands of Digital Designers

Dublin, Ireland - April 23, 2002 - Parthus Technologies (Nasdaq: PRTH, LSE: PRH), a leading provider of semiconductor platform-level intellectual property (IP), today announces the launch of a ...
Yahoo Finance

Cypress's New Family of High-Performance 4-PLL Clock Generators Simplify Design of Next-Generation Consumer and Networking Products

SAN JOSE, CA--(Marketwired - Feb 25, 2015) - Cypress Semiconductor Corp. (NASDAQ: CY) today introduced a high-performance programmable clock generator family that simplifies the design of consumer and ...