Electronics Weekly

Analysis: Open verification addresses chip complexity

Guest columnist Mark Glasser from Mentor Graphics believes that Open Verification Methodology, or OVM, is an attempt to bundle SystemVerilog interoperability with a standard library and a proven ...
Design-Reuse

Cadence Extends the Open Verification Methodology Beyond SystemVerilog to Include SystemC ...

SAN JOSE, Calif. -- Feb 23, 2009 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, today announced the release of open source libraries for e and ...
マイナビニュース

Mentor、UVM/OVMコンテンツを自社のオンラインアカデミーに追加

Mentor Graphicsは、Universal Verification Methodology(UVM)およびOpen Verification Methodology(OVM)を採用する企業がより多くの情報を必要としていることを受け、「Verification Academy」(先進機能検証技術に関する情報やオンライン・トレーニングを提供する同社のオンライン ...
CIOL

Cadence, Mentor make Open Verification available immediately

Distributed under the standard open-source Apache 2.0 license, the OVM source code, documentation and use examples may be downloaded free of charge. The OVM Web site is the central point of access for ...
Design-Reuse

Open Verification Methodology Helps KPIT Cummins Boost Productivity, Shorten Turnaround Time

The OVM, which Cadence Helped Develop, Enabled KPIT Cummins to Quickly Find Bugs in Its IP Design BANGALORE, India -- July 31, 2008-- Cadence Design Systems (I) Pvt Ltd., a subsidiary of Cadence ...
Business Insider

SmartDV Adds New Verification IP to Support OpenCAPI Standard

SAN JOSE, Calif., June 25, 2019 (GLOBE NEWSWIRE) -- SmartDV™ Technologies, the Proven and Trusted choice for Verification Intellectual Property (IP), added new Verification IP to support the OpenCAPI ...