EDN

SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator

SmartDVā„¢ Technologies announced support for Verilator, the free, open-source hardware description language (HDL) simulator, becoming the first Verification Intellectual Property (VIP) provider to do ...
New Electronics

Open-source SystemVerilog RISC-V processor functional coverage library

Imperas Software has announced the release of the first open-source SystemVerilog RISC-V processor functional coverage library for RISC-V cores. The initial release is for RV32IMC, RV64 and other ...
New Electronics

Cadence and Imperas support NSITEXE in development of automotive RISC V Vector processor IP

Imperas Software and Cadence Design Systems have collaborated to enable NSITEXE, part of the DENSO Corporation, to develop a RISC-V-based processor IP for functional safety and next-generation ...
Design-Reuse

Imperas leads the RISC-V verification ecosystem as the first to release an open-source SystemVerilog RISC-V processor functional coverage library

Complete source file access allows easy adoption and enables user extensions for advanced microarchitecture verification that helps all RISC-V projects accelerate time-to-market goals Design ...
Electronic Design

Cadence And Mentor Develop Open-Source SystemVerilog Methodology

EDA giants Cadence Design Systems and Mentor Graphics announced that they will create and standardize on a verification methodology based on the IEEE 1800(TM)-2005 SystemVerilog standard. Using the ...
Design-Reuse

Sibridge Technologies & Axiom Design Automation Partner to Integrate Verification IPs with SystemVerilog

Santa Clara & Milpitas, California, May, 25 2011: Sibridge Technologies, a leading provider of Design and Verification IPs, with expertise in ASIC/SoC design & verification and Embedded solutions and ...