The aim of this project is to write a VERIFICATION PLAN for a MOD-12 loadable up/down counter using SYSTEM VERILOG DIRECTORIES AND FILES the directories include env, env_lib, rtl, test, sim. env -> ...
This Repo contains the design flow for MOD-13, synchronous, binary ‘up’ counter (using TannerEDA software for simulation purposes). Design and Simulation done using S-Edit - An analog mixed-signal ...
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