GitHub

SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation

This repository contains the resources, code, and documentation supporting our work on training a model for HLS-C++ code generation. Our work demonstrates how to leverage transformer-based ...
Semiconductor Engineering

Challenges In Using HLS For FPGA Design

High-level synthesis (HLS) tools, which transform C/C++ source code to Verilog/VHDL, have been commercially available for over 15 years. HLS tools from FPGA vendors and EDA companies promise improved ...
Semiconductor Engineering

Optimize MATLAB C/C++ Code For HLS

A common use case for high-level synthesis (HLS) is taking 3rd party generated or legacy C/C++ algorithms and converting the algorithm to a hardware implementation using an HLS compiler. This can ...
GitHub

C_VLSI_HLS_Code/apint_arith_RTL.v

// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved. `timescale 1 ns / 1 ps (* CORE_GENERATION_INFO="apint_arith,hls_ip_2018_1,{HLS_INPUT_TYPE=c,HLS_INPUT ...
insideHPC

Gidel FPGA Tools Speed Development with Intel’s HLS

Today Gidel announced the availability of new development tools that take advantage of Intel’s HLS, producing a speed increase of 5x over prior development options. Intel’s High Level Synthesis (HLS) ...
IEEE

LLM vs HLS for RTL Code Generation: Friend or Foe?

Abstract: High-Level Synthesis (HLS) tools are widely used for the efficient transformations of behavioural code into equivalent hardware in Register Transfer Level (RTL). However, recent studies show ...
IEEE

HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks

Abstract: The rapid scaling of large language model (LLM) training and inference has accelerated their adoption in semiconductor design across academia and industry. Most prior works benchmark LLMs ...